1. Field of the Invention
The present invention relates to the field of hardware used for implementing arithmetic operations such as processor instructions. More specifically, the present invention relates to a binary shift right circuit for signed and non-signed binary values.
2. Related Art
Binary right shift circuits input multi-bit binary values and shift the bits to the right by a predetermined number of bits. By right shifting, the binary value is typically divided. For instance, a right shift by one bit position divides the original number by two. A right shift by three bit positions divides the original number by eight, etc. Generally, a right shift by n bit positions will divide the original number by 2.sup.n. Right shift circuits of the prior art ignore the bits that are shifted out of the original binary value (e.g., truncates the result) and zeros are typically shifted into the right side, which is also called the most significant bit (MSB) position. Many arithmetic functions utilize the right shift operation and, in practice, arithmetic logic units (ALUs) of hardware processors always contain one or more right shift hardware units. One such arithmetic operation that utilizes the right shift operation is used in conjunction with processing Motion Picture Expert Group (MPEG) digital data.
The basic steps in MPEG compression and decompression processes are based around computationally demanding functions such as the Inverse Discrete Cosine Transform (IDCT) function, the Discrete Cosine Transform (DCT), Quantization and Motion Compensation functions. All of these functions require operations that shift, average, and/or divide multiple operands. For instance, a software MPEG decoder performs the IDCT function and Motion Compensation processes. More specifically, the IDCT function transforms the MPEG encoded coefficients back to their pixel values. In some decoders, an integer processor is preferred for performing IDCT and Motion Compensation functions because it is faster than a floating point processor.
However, the use of integer processors in the MPEG decoder requires conversion of the floating point values into binary integer values. Specifically, in one operation, a 12-bit range coefficient is input (integer) but the pixel values generated by the decoder are in the 9-bit range. Computations are performed using 16-bit operations to avoid any overflow problems. In this particular MPEG decoding process, a prescaling step is performed where the input value is left shifted by 3 bits to preserve precision in the 16-bit operations that follow the prescaling step. In the end, the result is then right shifted to accommodate the 9-bit output and to compensate for the prescaling operation.
Unfortunately, the right shift circuits of the prior art truncate their results, e.g., discarding the bits that are shifted out of the LSB (least significant bit) positions. This is disadvantageous because one of the main objectives of MPEG processing is to retain a high image quality. Another attribute of MPEG processing is that fast computations need to be performed because the MPEG data is typically large and transmitted isochronously. Therefore, computational latencies can produce unwanted artifacts (e.g., image jitter, etc.) in the audio/visual playback. In order to maintain high data precision and image quality, it would be advantageous to provide a right shift circuit that does not discard these truncated bits, yet does not require additional latencies in the computation. The present invention provides these advantages.